In EECS470, groups of 4-5 people design from the ground-up an out-of-order processor with the Alpha ISA in Verilog. Here is the project specification: Page on Umich
The baseline project is difficult, but probably "only" requires around 40-60 hours a week. However, as the performance part of the grade (20%) is curved to the class, there has been an "arms race" to see which group can design the fastest processor, ever regardless of year. Taking this arms race seriously probably resulted in 60-80+ hours of work. Back when I took it, it was impossible to avoid this arms race unless you were content with not receiving an A in the class although you could still get an A by performing extremely well on the exams. As a senior level course, EECS470 was also cross-listed as an introductory graduate level course, which meant that scoring well on the exams was a much more difficult proposition than in lower level courses due to the competition.
For those with no knowledge in processor design, an aggressive EECS470 project is similar at a high level to a commercial ARM A12 minus the uncore, some of the ISA-specific difficulties, I/O, coherency, and a heck of a lot of performance tuning. How is a team of 5 newbies supposed to design something that takes a team of hundreds of people several years to do so? Simple: Alpha is a very easy ISA, the EECS470 project is not optimized for area, performance, and clock speed, and most importantly: everyone's EECS470 project contains many bugs!
In EECS427 VLSI, groups of 4-5 people design, place, and route from the ground-up an in-order processor with a simple 16-bit custom ISA. The main difficulty is that the processor datapath is full custom, which means that every transistor is sized, laid out, and connected to other transistors by hand. For comparison purposes, in the UT Austin version of this class, only a small SRAM and an adder is assigned for custom layout. As in EECS470, there is again a major arms race in this class, but this is for a $1500 cash prize. Back when I took the class, my group participated in this arms race with gusto. The previous clock speed of 650MHz was held by the TA of the class. He smugly told us that it would be impossible for us to break this record. Of course, we took it upon ourselves to do exactly that, reaching a record-shattering 1.05GHz clock speed. In addition, we chose to implement 4-way SIMD as our special feature. Every member of our group worked for roughly 80-100 hours a week (a conservative estimate) solely on this project to make this happen.
To learn about how we did this, you can read our project report: Page on Appspot
Webpage about our accomplishment: EECS News
After that semester, the professor banned some of the techniques that we used, thus ending the war on clock speed and preserving our title for life :)
Read other answers by Dan Zhang on Quora:
- Why are grad schools often reluctant to take their own students?
- How do top students or studious students show off in class?
- How common (or uncommon) is it for PhD students to feel relatively stupid compared to the graduate (M.S) or undergraduates they usually work with?
from Quora http://ift.tt/2dl4M7T
